1. Field of the Invention
The present invention relates to a method and apparatus for imposing onto an incoming signal a time delay the magnitude of which is digitally programmable, and more particularly to a method and apparatus for producing the time delay as a summation of a series of smaller delays to maximize the frequency at which delays may be digitally programmed.
2. Description of the Related Art
Digital delay generators are commonly employed in instrumentation, automated test equipment and communications contexts. A typical automated test application involves the introduction of a variable delay to a timing edge which is then supplied to a circuit under test. The circuit can be observed to ascertain the effect of the delay on its operation.
A typical communications application involves the transmission of data encoded in the phase modulation of a periodic waveform. The phase of the periodic waveform is varied as a direct function of the numerical value of a digital word comprising a digital data stream. Thus, the information transmitted as a digital data stream is encoded in the phase of the periodic waveform, the periodic waveform being less susceptible to distortion during transmission over long distances. As an example, various phase modulation formats are employed by modern computer modems to transmit digital data streams over telephone lines.
Generally, a digital delay generator is an electronic circuit which receives as inputs: an incoming input signal the timing edges of which are to be delayed, and a digital data stream the numerical values of which define the magnitude of the delay for each period or timing edge (i.e. rising edge) of the input signal. The delay generator provides an output which is essentially the input signal with its periods or timing edges delayed in accordance with binary values encoded within the digital data stream. The data stream is typically organized into digital words comprising multiple bits so that a plurality of possible delay values can be encoded for each period or timing edge of the incoming waveform.
An illustration of a generic digital delay generator used to modulate the phase of a periodic waveform is illustrated with reference to FIGS. 1a, 1b and 1c. FIG. 1a is a block diagram depiction of a generic prior art digital delay generator 10. The periodic waveform to be delayed (i.e. modulated) is a pulse train V(t) which is fixed in frequency and is present at input 12 of delay generator 10. The pulse train input 22 is illustrated in FIG. 1c. A digital data stream D(k) representing the binary information to be encoded as delays in the periodic waveform is presented at input 14 of delay generator 10, and is represented in FIG. 1c as waveform 26.
With each rising edge (i.e. timing edge) of the period waveform 22 at input 12 of delay generator 10, a new digital word D(k) comprising N bits from data stream 26 is read into the delay generator 10 through input 14. The leading or timing edge of each pulse then appears at output 13 of delay generator 10, subject to a delay (.tau.), the magnitude of which is proportional to the value of the digital word D(k) read from digital data stream 26 and which is associated with that timing edge. The delayed output is illustrated in FIG. 1c as waveform 24. The output is represented as V(t+.tau.), where .tau. for a given value of D(k) is equal to .tau..sub.min +D(k)q. .tau..sub.min is the minimum delay through the circuit due to circuit propagation delay and q is the resolution of the delay circuit. This relationship is illustrated in FIG. 1b.
FIG. 1c illustrates the relationship between the incoming waveform V(t) 22 and the output waveform V(t+.tau.) 24. Each timing or rising edge of V(t) 12 is delayed by some delay 28 that corresponds to the value of D(k) 26 at the time the edge entered the Delay Generator 10.
Typical digital delay generators are implementable in numerous circuit configurations and in numerous circuit technologies used for manufacturing integrated circuits, including complementary metal-oxide-semiconductor (CMOS), silicon bipolar and gallium arsenide.
A typical implementation of a prior art delay generator, sometimes known as a ramp delay generator, is illustrated in FIG. 2a. An incoming waveform V(t) 80 is presented at the input of a ramp generator circuit 82. The incoming waveform 80 can be a pulse train as shown in FIG. 2b. Ramp generator 82 is triggered to produce a ramping output voltage V.sub.R 96 (FIG. 2b) by each timing edge (i.e. a rising edge) of pulse train 80, as the magnitude of V(t) 80 exceeds some threshold value. Just prior to each timing edge of incoming waveform 80, one or more bits of data stream D(k) 90 (FIG. 2b) are latched into digital-to-analog converter (DAC) 92. DAC 92 then outputs a voltage V.sub.DAC 98 which is (virtually) linearly proportional to the binary value of the input word D(k) 90. V.sub.DAC 98 is presented to the negative input of Comparator 84 and V.sub.R 96 is presented to the positive input of Comparator 84.
While V.sub.R 96 remains less than the magnitude of DAC output voltage V.sub.DAC 98, the output voltage V(t+.tau.) 86 of comparator 84 remains low. When the magnitude of ramping output voltage V.sub.R 96 exceeds DAC output voltage V.sub.DAC 98, comparator output voltage V(t+.tau.) 86 switches high and remains high until the ramp generator circuit 82 is reset, causing the magnitude of its output voltage V.sub.R 96 to return to zero.
Because the magnitude of ramp generator output voltage V.sub.R 96 is virtually linear with respect to time (i.e. V.sub.R =dv/dt (.DELTA.t)), its amplitude is directly proportional to the time which has elapsed since the ramp generator 82 was last triggered by a timing edge. Thus, DAC 92 controls the magnitude of the delay imposed on a timing edge of incoming waveform 80 to create output waveform V(t+.tau.) 86 as a function of the binary value of the input word D(k) 90 through V.sub.DAC 98. The operation of the ramp delay generator of FIG. 2a is illustrated by the waveforms of FIG. 2b.
For virtually any delay generator, there will always be some minimum delay .tau..sub.min introduced between the timing edges of an input waveform and the output waveform due to circuit propagation delays. For the ramp delay generator of FIG. 2a, even if D(k) 90 is a binary zero such that V.sub.DAC 98 is zero and the ramp time is virtually zero, there will be a delay (.tau.=.tau..sub.min) associated with the propagation of the incoming waveform through the circuitry comprising the ramp generator 82 and Comparator 84. Thus, the programmable delay of a delay generator is the net delay .tau..sub.net =.tau.-.tau..sub.min, and its programmable delay range .tau..sub.R is equal to the difference between its maximum delay (.tau..sub.max) and its minimum delay (.tau..sub.min).
The fastest rate at which a delay generator can be reprogrammed with a digital word representing a new delay value is typically referred to as the maximum reprogramming rate. For the ramp delay generator of FIG. 2a, ramp generator circuit 82 cannot be retriggered until, at a minimum, a time equal to the maximum programmable delay range .tau..sub.R =.tau..sub.max -.tau..sub.min has elapsed. Ramp generator 82 also cannot be retriggered until the value of V.sub.DAC 98 corresponding to the new value of D(k) 90 has settled sufficiently to provide an accurate and stable switch point for Comparator 84. Finally, the ramp generator 82 cannot be retriggered until it has been completely reset to zero upon completion of the previous delay period.
Typically, the DAC settling time .tau..sub.DAC 97, FIG. 2b is equal to or greater than the ramp generator reset time .tau..sub.reset 99, FIG. 2b, so that the maximum reprogramming rate is equal to 1/(.tau..sub.R +.tau..sub.DAC) The greater the number of bits comprising the input word, the greater the time necessary for the DAC to accurately translate the word into a stable V.sub.DAC value 98.
Because a new timing edge of incoming waveform 80 cannot enter until some finite time (i.e. the greater of .tau..sub.reset and .tau..sub.DAC) after the ramp time reaches the maximum delay range, delay generators such as that of FIG. 2a cannot be operated with a delay range that spans minimum reprogram time without using multiples of such delay circuits in parallel. Such an arrangement greatly increases system complexity. Further, because .tau..sub.DAC is typically greater than .tau..sub.reset, DAC 92 must be very fast and very accurate for a ramp delay generator to achieve high speed performance with reasonable accuracy.
There is a need in the art for delay generators which have higher programming rates and where the programmable delay range equals or exceeds the minimum reprogram time. For example, in the area of data communications, the higher the frequency of the periodic or carrier waveform, the more digital information can be transmitted per unit time. The delay generator, however, must be capable of being programmed at a rate which is substantially equal to or greater than the higher frequency carrier. In another example, test applications may require timing edges to be delayed beyond the desired minimum reprogram time.
Other delay generator performance criteria of interest include the setability (i.e. how finely the delays may be programmed) and accuracy of the resulting delays. Accuracy can be improved if the system has the ability to be calibrated externally. To achieve higher programming rates, prior art delay generators such as the one in FIG. 2a have employed expensive high-speed DAC's capable of maintaining reasonable resolution, linearity and accuracy over the desired delay range, while converting larger binary words into a greater number of threshold voltages. High speed, high resolution DAC's, however, can be costly.
Another technique used in the past to increase programming rates of prior art delay generators is to employ a number of delay generators in parallel as conceptually illustrated in FIG. 3a. This technique is also costly as a result of circuit complexity. Further, this technique is limited by the speed at which the decoding process takes place.
Finally, an attempt has been made to create a desired delay range over a serial delay line as illustrated in FIG. 3b. The delay line is made up of a series of cells 70, each of which has a fixed maximum delay 72 interposed in one of two paths, and a fixed minimum delay 74 interposed in a second path. Each cell includes a 2:1 multiplexer 76 to choose between the two paths through the cell. A digital control input 71 is provided to control the MUX, and each cell's control input is coupled to one of the bits of a digital control word D(k) 73. The fixed maximum delay of each cell is weighted in accordance with the binary weight of its control bit such that each cell provides its weighted fraction of the total desired maximum delay of the delay line.
There are a number of problems associated with this implementation. First, the delay range of the line is fixed and cannot be changed externally in real time. Second, external calibration of the line is not possible. Third, this implementation of a serial delay line cannot be configured to permit reprogramming times less than the established delay range. Finally, glitches can result from improper timing between signals on the control input and the incoming timing edges, thus interfering with the integrity of the incoming waveform as it propagates through the line. An example of such a serial delay line is sold by Motorola, Inc., known as the 10E195. A more detailed description of this product can be found in the Motorola Eclipse Data Book.